1. Field of the Invention
This invention relates to sense amplification in data memories.
2. Description of the Prior Art
Many random access memories (RAMs) use sense amplifiers for fast reading of stored data. This applies to dynamic RAM, static RAM, cache RAM and almost any embedded RAM structures which are designed for moderate to high speed.
In such memories, a part of a memory address supplied to the RAM is generally used to select and activate one of a plurality of rows of memory cells; the outputs of the memory cells in the activated row are connected in parallel via bit-lines to the inputs of the sense amplifiers.
A RAM read or write cycle may be initiated either by placing a new address on an address input of the RAM (which is usually the case for individual RAM chips) or by a transition in a clock or other control signal (which is generally the case for a RAM in an embedded controller device). A number of events then take place. Firstly, a state of RAM pre-charge is disabled, releasing the RAM from an idle condition and priming it for an active read or write operation. At the same time, or very shortly after, a row decoder starts to decode the input address, in order to generate a unique row-line output. For a medium sized RAM this may involve decoding eight address inputs to select one of 256 row control lines. After the row control line has been selected, all of the memory cells which are controlled by that row control line are activated, and those particular memory cells can be read-from or written-to.
In the case of a read cycle, the selected memory, cells begin to charge or discharge bit-lines connecting the memory cells to the respective sense amplifiers, and subsequently the charge currents or resulting voltage changes on the bit-lines are detected by the sense amplifiers. The outputs of the sense amplifiers (i.e. the data output of that row of the RAM) are written to the system or output data bus via a powerful buffer. Between the bit-lines and the sense amplifier there may also be a multiplexing stage (column decode) which further reduces the selection of RAM cells before presentation at the sense amplifier inputs, though this stage is often absent; column decoding is often enabled at the same time as row decoding.
The sense amplifiers are used to detect and amplify small changes in output (bit-line) current or voltage when a single RAM cell is enabled onto a bit-line, and they may take the form of current sensing amplifiers or voltage sensing amplifiers. Balance points are chosen to react quickly to small input changes; as a consequence the sense amplifiers are biassed with relatively large dc currents.
Once a sense amplifier has detected a small input change and amplified it to full logic levels, then some form of output device is required to propagate the RAM data. For a stand-alone dynamic or static RAM integrated circuit, this output device or driver may be an input/output pad which is designed to drive onto a printed circuit board in a data processing system. For an embedded cache or cache RAM, the output may be driven onto a common shared data-bus. In both cases the load capacitances are very high, and so the output buffer needs high current drive, which again implies a high power dissipation.
A further disadvantageous feature of sense amplifier operation is the power dissipated by pre-charge or equalisation "glitches" (transient spurious signals) applied to the output load capacitance of the sense amplifier. These glitches result from a common feature of fast sense amplifier designs known as "internal pre-charge", where the internal circuit nodes within tee sense amplifier are pre-set to a certain logic value, or equalised. Internal pre-charging leads to a rapid settling time when a new input is presented to the sense amplifier. However, a drawback of the use of internal pre-charging or equalisation is that the sense amplifier can initially output one value, and then quickly over-write it with a new value once sensing has taken place.
An example is illustrated by the case of a sense amplifier whose internal pre-charged value is logic-`0`. This means that if the RAM is in the idle phase and the sense amplifier is enabled at the beginning of a read cycle, then the amplifier will initially output a logic-`0`. Once recording is initiated, the sense amplifier inputs will change so that the output will be driven to either logic-`1` or logic-`0`. Clearly there is no problem if the final read value is logic-`0` because the sense amplifier has already produced that answer. However, the worst case is for a logic-`1` output, where initially the sense amplifier will output a logic-`0` due to the internal pre-charging, followed by a logic-`1` due to the presence of real data at the sense amplifier's inputs.
RAM output data are commonly latched to preserve output levels between successive read cycles, so if the old RAM value was logic-`1` and the new value is also logic-`1` then the output would pass through the rapid sequence of `1-0-1`, where the logic-`0` level is a temporary glitch whose duration equals the interval between the time of turning on the sense amplifier and the time at which the new data are sensed.
The output glitch described above is clearly wasteful of power, particularly if the RAM outputs propagate the glitch to a high-capacitance printed circuit board or main system bus.